`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:52:39 10/30/2011 
// Design Name: 
// Module Name:    VGA_Writer 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module VGA_Sync(clk, reset, vga_v_sync, vga_h_sync);

input clk;
input reset;
output vga_h_sync, vga_v_sync;


//////////////////////////////////////////////////
reg [9:0] CounterX=0;
reg [8:0] CounterY=0;
wire CounterXmaxed = (CounterX==10'h2FF);

always @(posedge clk)
if(reset) begin
	CounterX<=0;
	end
else if(CounterXmaxed)
	CounterX <= 0;
else
	CounterX <= CounterX + 1;

always @(posedge clk)
if (reset) 
	CounterY <= 0;
else if(CounterXmaxed) CounterY <= CounterY + 1;



reg	vga_HS, vga_VS;
always @(posedge clk)
begin
	vga_HS <= (CounterX[9:4]==6'h2D); // change this value to move the display horizontally
	vga_VS <= (CounterY==500); // change this value to move the display vertically
end

	
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;

endmodule
